The present invention relates to a phase change memory device and a method for manufacturing the same, and more particularly, to a phase change memory device in which a phase change layer is stably formed and is prevented from lifting, and a method for manufacturing the same.
In general, memory devices are largely divided into a volatile RAM (random access memory), which loses inputted information when power is interrupted, and a non-volatile ROM (read-only memory), which can continuously maintain the stored state of inputted information even when power is interrupted.
When considering volatile RAM, a DRAM (dynamic RAM) and an SRAM (static RAM) can be mentioned, and when considering non-volatile ROM, a flash memory device such as an EEPROM (electrically erasable and programmable ROM) can be mentioned.
As is well known in the art, while the DRAM is an excellent memory device, the DRAM must have high charge storing capacity, and to this end, since the surface area of an electrode must be increased, it is difficult to accomplish a high level of integration. Further, in the flash memory device, due to the fact that two gates are stacked on each other, a high operation voltage is required when compared to a source voltage. Accordingly, a separate booster circuit is needed to form the voltage necessary for write and delete operations, making it difficult to accomplish a high level of integration.
To improve upon the current memory devices, researches have been actively making an effort to develop a novel memory device that has a simple configuration and is capable of accomplishing a high level of integration while retaining the characteristics of the non-volatile memory device. A phase change is memory device recently disclosed in the art is a product of this effort.
In the phase change memory device, a phase change, which occurs in a phase change layer interposed between a lower electrode and an upper electrode, from a crystalline state to an amorphous state is due to current flow between the lower electrode and the upper electrode. The information stored in a cell is recognized by the medium of a difference in resistance between the crystalline state and the amorphous state. In detail, in the phase change memory device, a chalcogenide layer, being a compound layer made of germanium (Ge), stibium (Sb), and tellurium (Te), is employed as a phase change layer. As a current is applied, the phase change layer undergoes a phase change by heat, that is, Joule heat, between the amorphous state and the crystalline state. Accordingly, in the phase change memory device, when considering the fact that the specific resistance of the phase change layer in the amorphous state is higher than the specific resistance of the phase change layer in the crystalline state, in a read mode, whether the information stored in a phase change cell has a logic value of ‘1’ or ‘0’ is determined by sensing the current flowing through the phase change layer.
It is known that, since the phase change memory device has a simple structure, and adjoining cells do not interfere with each other, a high level of integration is possible. Also, since the phase change memory device has a read speed of several tens of ns (nano second) and a relatively high write speed of several tens to several hundreds ns, high speed operation is possible.
Additionally, because the phase change memory device has excellent applicability to the conventional CMOS logic processes allowing manufacturing costs to be reduced, the phase change memory device is regarded as a memory device that is highly advantageous in terms of commercialization.
However, when considering phase change memory devices of the prior art, in the course of depositing a phase change material, that is, in the course of depositing a phase change material layer on an insulation layer, the phase change material layer is likely to be poorly deposited on the insulation layer, and even if the phase change material layer is deposited, when conducting subsequent processes lifting of a phase change layer is likely to occur.